1. Field of Application
The present invention relates to a TAD (Time Analog-to-Digital) type of A/D (Analog-to-Digital) converter, in which A/D converted data are obtained as respective values each expressing a number of stages of a series of delay units that have been traversed by a pulse signal during a measurement interval.
2. Description of Related Art
Various TAD types of A/D converters have been proposed, for example as described in Japanese patent first publication No. 5-259907 (referred to in the following as related document 1), in which a pulse delay circuit formed of a plurality of series-connected stages (with each stage made up of a delay unit) delays a pulse signal by an amount that is determined by (e.g., is inversely proportional to) the voltage level of an analog input signal, and in which A/D converted data are outputted as numeric values each expressing the voltage level of the analog input signal as the number of delay stages that are traversed by the pulse signal during a sampling interval. That number of stages can be obtained by simultaneously registering (e.g., using a latch circuit) the respective output signal values from the delay units at the end of the sampling interval, to thereby detect the position attained by the pulse signal within the pulse delay circuit up to that time point.
In addition as described in documents such as Japanese patent first publication No. 2004-7385 (referred to in the following as related document 2), rather than forming the pulse delay circuit as a linear delay line formed of a set of series-connected stages, the output signal from the final delay unit is transferred to a first input terminal of the first-stage one of a set of series-connected delay units, to form a ring-configuration delay line. With such an A/D converter, a pulse signal circulates continuously around the ring delay line formed by the pulse delay circuit. In each interval between successive sampling time points, a circulation number counter counts the total number of times the pulse signal circulates around the pulse delay circuit. At each sampling time point, the stage reached by the pulse signal within the pulse delay circuit (i.e., the respective output signal states of the delay stages) and the count value of the counter are registered, in respective latch circuits.
Hence, at each sampling time point, a digital numeric value is obtained that is made up a set of high-order bits which are based on the count value attained by the circulation number counter and a set of low order bits expressing the position reached by the pulse signal within the pulse delay circuit. Each A/D converted output value is obtained based on the difference between the currently obtained numeric value and the immediately previously obtained numeric value (read out from the latch circuits).
Another related example is described in Japanese patent first publication No. 2004-357030 (referred to in the following as related document 3), whose principles are based on those of the A/D converter of related document 2 above (i.e., using a pulse delay circuit formed of delay units that are connected as a ring delay line, and a circulation number counter). With that example, instead of detecting the number of delay stages that have been traversed by the pulse signal, at a single sampling time point in each conversion operation, that number is detected n times in succession in each conversion operation, (where n is an integer), at a plurality of sampling time points that successively differ in time by 1/n times the amount of delay that is currently being applied by each delay unit. In each conversion operation, the respective numeric values obtained at the n successive detection time points are summed, to obtain a numeric value having a higher resolution than is obtained when only a single detection operation is performed in each conversion operation. As described above, each output A/D converted value is obtained as the difference between the currently obtained numeric value and the immediately preceding (latched) numeric value.
Such a method (which is also described in reference document 2) provides increased speed of conversion and increased A/D conversion resolution.
With the A/D converter of reference document 1, control signals that determine the timings for activating the pulse delay circuit and determine the timings at which the respective output signal states of the stages of the pulse delay circuit registered by a latch circuit, are derived using a counter that counts a system clock signal (used as a sampling clock signal) and a decoder that decodes the count values of the counter, to obtain the control signals. In general, the period of such a system clock signal is made comparatively long, in order to ensure stable operation of the digital circuits.
With such an A/D converter, it is necessary to ensure that when the states (i.e., output signals) of the stages in the pulse delay circuit have been registered (i.e., latched), a sufficiently long waiting interval elapses before the pulse delay circuit is again activated to initiate traversing of the pulse delay circuit stages by a pulse signal. This is necessary to ensure that the “new” pulse signal will not be initiated before the “old” (i.e., previously initiated) pulse signal has been outputted from the final stage of the pulse delay circuit.
However with the A/D converter of reference document 1, the timings of a sampling clock signal for latching the states of the stages in the pulse delay circuit at respective sampling time points, and the timings of an activation control signal for periodically initiating a pulse signal, can only be determined based on the system clock signal. Thus, the aforementioned waiting interval can only have a value that is the inverse of the system clock frequency multiplied by an integer.
Hence, it is not possible to arbitrarily select that waiting interval to have a value that is the minimum necessary for ensuring stable operation of the A/D converter (i.e., a value which is only slightly longer than the maximum time required for a pulse signal to traverse all of the stages of the pulse delay circuit). Thus, the waiting interval must be made unnecessarily long, so that the A/D conversion rate (sampling rate) is correspondingly lowered.
The general configuration of an A/D converter having a ring delay line and a counter circuit that counts the number of circulations of a pulse signal around the ring delay line, as described in reference documents 2 or 3 is illustrated in FIG. 20, designated by numeral 100. Only the circuit sections necessary for detecting the output signal states of the stages of the pulse delay circuit at a single sampling time point in each conversion operation are shown. With such an A/D converter, after a pulse signal has been initiated by an activation control signal RR, the pulse signal continuously circulates around the pulse delay circuit 101. At each sampling time point defined by a sampling clock signal CKS, the states of the output signals from the pulse delay circuit 101 and the count value reached by the circulation counter circuit 103 are registered in the latch and encoder circuit 102 and latch circuit 104 respectively. In the latch and encoder circuit 102, the latched-in data (i.e., expressing the stage in the pulse delay circuit 101 reached by the pulse signal at the sampling timing) are decoded to obtain the low-order bits (indicated as “a” in FIG. 20) of a corresponding numeric value, while the count value of the circulation counter circuit 103, registered in the latch circuit 104, expresses the high-order bits (indicated as “b”) of that numeric value. At the next sampling time point, the bits of the newly derived numeric value are registered in a latch 110.
At each sampling time point, the immediately previously obtained numeric value (indicated as DTn−1) is read out from the latch 110 and subtracted from the currently obtained numeric value (indicated as DTn), by a subtractor 112, to obtain an output A/D conversion data value expressing the total number of stages in the pulse delay circuit 101 that have been traversed by the pulse signal since the preceding sampling time point, with that value indicated as DT in FIG. 20.
More specifically, if the currently obtained numeric value DTn is lower than the immediately previously obtained numeric value DTn−1 (thereby indicating that overflow of the circulation counter circuit 103 has occurred, since the preceding sampling time point) then the subtraction operation is performed as {(DTn+k)−DTn−1}, where k is the maximum count value of the circulation counter circuit 103. If DTn is higher than DTn−1 then the subtraction operation is performed as {DTn−DTn−1}. This operation is illustrated in the graph and timing diagram of FIG. 6 in related document 2, in which the values designated as “IS” correspond to successively derived ones of the values DT of FIG. 20 described above.
Thus with such a TAD type of A/D converter, although a high rate of A/D conversion speed can be achieved, there is the disadvantage that it is necessary to incorporate additional latch and subtractor circuits, causing the overall circuit scale to be substantially increased.